1. Field of the Invention
The present invention relates generally to a data flow type information processor and a data processing method in the information processor, and more particularly, to a data flow type information processor including an external storage and a data processing method in the information processor.
2. Description of the Background Art
In a conventional von Neumenn computer, various instructions are stored in advance as programs in a program memory, and addresses in the program memory are sequentially specified by a program counter so that the instructions are sequentially read out, whereby the instructions are executed.
On the other hand, a data flow type information processor is one type of a non-von Neumenn computer having no concept of sequential execution of instructions by a program counter. Such a data flow type information processor employs architecture based on parallel processing of instructions. In the data flow type information processor, immediately after data which are objects of an operation are collected, an instruction can be executed and a plurality of instructions are simultaneously driven by the data, so that programs are executed in parallel in accordance with the natural flow of the data. As a result, it is considered that the time required for executing operations is significantly reduced.
FIG. 1 is a block diagram showing one example of a structure of a conventional data flow type information processor, and FIG. 2 is a diagram showing one example of a field structure of a data packet processed by the information processor.
Referring now to FIGS. 1 and 2, description is made of a structure and a schematic operation of the conventional data flow type information processor. A destination field in the data packet shown in FIG. 2 stores destination information, an instruction field stores instruction information, and a data 1 field or a data 2 field stores operand data.
In FIG. 1, a program storing portion 1 includes a program memory (not shown). A data flow program including destination information and instruction information is stored in the program memory, as shown in FIG. 3. The program storing portion 1 reads out one of the destination information and one of the instruction information by addressing based on the destination information of the data packet, stores the information in the destination field and the instruction field of the data packet, respectively, and outputs the data packet.
A paired data detecting portion 2 queues data packets inputted from the program storing portion 1. More specifically, the paired data detecting portion 2 detects two data packets having the same destination information, stores operand data of one data packet in a predetermined data field of the other data packet, and outputs the other data packet. On this occasion, the above described one data packet disappears. An operation processing portion 3 decodes the instruction information of the data packet inputted from the paired data detecting portion 2, performs predetermined operation processing with respect to the operand data therein, stores the result of the operation processing in the data field of the data packet, and outputs the data packet to a branch portion 4.
The branch portion 4 outputs the data packet to an internal data buffer 5 or an external data memory 6 based on the destination information in the data packet. The data packet outputted from the internal data buffer 5 or the external data memory 6 is applied to a merge portion 7. The merge portion 7 applies the data packets to the program storing portion 1 in the order of arrival.
In the data flow type information processor shown in FIG. 1, the data packet continues to circulate through the program storing portion 1, the paired data detecting portion 2, the operation processing portion 3, the branch portion 4, the internal data buffer 5 or the external data memory 6 and the merge portion 7, so that operation processing based on the program stored in the program storing portion 1 progresses.
FIG. 4 is a diagram showing a schematic structure of the program storing portion 1 shown in FIG. 1. In FIG. 4, an input data latching portion 11 holds destination information in a data packet. On this occasion, instruction information disappears. Meanwhile, the input data latching portion 11 latches operand data. The destination information latched in the input data latching portion 11 is applied to an address calculating portion 12. In the address calculating portion 12, an address in a program memory 13 is calculated based on the destination information. The program memory 13 stores the data flow program including the destination information and the instruction information as shown in FIG. 3. New destination information and instruction information read out from the program memory 13 in response to the above described address are applied to an output data latching portion 14, to be latched therein. Meanwhile, the output data latching portion 14 latches the operand data latched in the input data latching portion 11 without any modification.
A plurality of data flow type information processors each having the above described structure are coupled to each other, to constitute a multiprocessor system. If and when a data packet outputted from an external data memory 6 in one information processor is sent to another information processor in this multiprocessor system, the data packet must pass through a path for internal processing. More specifically, the data packet outputted from the external data memory 6 is sent to another information processor from a branch portion 4 through a merge portion 7, a program storing portion 1, a paired data detecting portion 2 and an operation processing portion 3. Thus, internal processing through an internal data buffer 5, the program storing portion 1 and the like and processing from the external data memory 6 to the exterior are merged in the merge portion 7. Therefore, the speed of the internal processing and the speed of the processing to the exterior are reduced.
Therefore, it is considered that an output of an external data memory 6 is directly connected to another information processor without passing through a merge portion 7 as shown in FIG. 5. In this case, internal processing through an internal data buffer 5, a program storing portion 1 and the like and processing from the external data memory 6 to the exterior are not merged. However, the problem occurs in that a data packet processed by the external data memory 6 cannot be directly used in the internal processing without passing through another information processor.
Additionally, if and when a data packet is sent to one information processor from another information processor and sent to still another information processor in this multiprocessor system, the data packet is inputted to a merge portion 7 and outputted from a branch portion 4. Thus, the data packet always passes through the program storing portion 1, a paired data detecting portion 2 and an operation processing portion 3. Therefore, internal processing in which a data packet passes through the internal data buffer 5 or the external data memory 6 and processing in which a data packet is sent from the exterior to the exterior are merged. Consequently, additional time is required for sending an externally applied data packet to still another information processor, which delays the internal processing.